1. Field of the Invention
The present invention pertains to a solid-state photographic element having a plurality of pixels. More particularly, this invention pertains to a solid-state photographic element that can perform electronic shutter action simultaneously for a plurality of pixels.
2. Description of the Related Art
To increase the sensitivity of solid-state photographic elements, a signal amplification, junction field-effect transistor (JFET) may be installed in pixel units in the photographic elements. These are called amplification type solid-state photographic elements. A prior art photographic element includes a photoelectric converter separated from the amplifying transistor and a transfer gate, located between the photoelectric converter and the transistor, that controls transfer of charges (i.e., potential) from the photoelectric converter to the amplifying transistor.
FIG. 6 is a schematic circuit diagram of a prior art amplification type solid-state photographic element. FIG. 7 is a pulse timing chart that illustrates the operation of the schematic circuit diagram shown in FIG. 6.
As shown in FIG. 6, each pixel 31 (only one of nine shown pixels is labeled with reference numbers) is comprised of a transfer control element (a p-channel MOSFET) 31a, a photodiode 1 that generates and accumulates a charge according to incident light, and a JFET 2 that generates a signal output according to the charge received at its control region (the gate). The transfer control element 31a includes a transfer gate electrode TG for controlling transfer of the charge generated and accumulated by photodiode 1 to the control region of JFET 2. A reset element (p-channel MOSFET) 31b having a reset drain R.sub.D, is provided for discharging the charge transmitted to the control region of JFET 2. Reset gate R.sub.G is a reset control for controlling reset drain R.sub.D.
The source of each JFET 2 is connected in common to vertical source lines 32a, 32b, and 32c for each column of the matrix layout. A common drain power source 31c for the all pixels is connected to the drain of each JFET and the cathode side of photodiode 1 by a pattern, or diffusion, layer not represented in the figure. In addition, the control region (gate) of JFET 2 is connected to the drain of transfer control element 31a and the anode side of each photodiode 1 is connected to the source of element 31a.
Transfer gates (transfer gate electrodes) T.sub.G of transfer control elements 31a are connected in common to respective clock lines 33a, 33b, and 33c that scan under control of a vertical scanning circuit 34 for each row of the matrix layout. When drive pulses .phi..sub.TG1 to .phi..sub.TG3 are delivered from vertical scanning circuit 34, transfer control elements 31a operate in sequence for each row of pixels.
The reset drains R.sub.D of the reset elements 31b are connected in common to clock lines 50a, 50b, and 50c that scan under control of the vertical scanning circuit 34 for each row of the matrix layout. Reset gates (reset gate electrodes) R.sub.G are connected in common for all pixels to drive pulse generating circuit 37 by way of row line 37a. In addition, the source of reset element 31b is the same as the drain of transfer control element 31a. Moreover, this is designed such that this reset element 31 b operates when drive pulse .phi..sub.RG delivered from drive pulse generating circuit 37 is applied to the reset gates R.sub.G.
Each of vertical source lines 32a, 32b, and 32c is connected to the electrodes of each of light signal output accumulating capacitors (second memory elements) C.sub.S1, C.sub.S2, and C.sub.S3 by way of light signal output transmitting MOS transistors T.sub.S1, T.sub.S2, and T.sub.S3, and to dark signal accumulating capacitors (first memory elements) C.sub.D1, C.sub.D2, and C.sub.D3 by way of dark output transmitting MOS transistors T.sub.D1, T.sub.D2, and T.sub.D3. Respectively, the MOS transistors T.sub.S1, T.sub.S2, and T.sub.S3 and second memory elements C.sub.S1, C.sub.S2, and C.sub.S3, and MOS transistors T.sub.D1, T.sub.D2, and T.sub.D3 and first memory elements C.sub.D1, C.sub.D2, and C.sub.D3 are connected to signal output line 38 and dark output line 39 via horizontal read select MOS transistors T.sub.HS1, T.sub.HS2, T.sub.HS3, T.sub.HD1, T.sub.HD2, and T.sub.HD3. Moreover, generally, parasitic capacitors C.sub.HS and C.sub.HD are present on signal output line 38 and dark output line 39, respectively. In addition, buffer amplifiers 38a and 39a are connected to signal output line 38 and dark output line 39, respectively.
Signal output line 38 and dark output line 39 are also connected to the drains of horizontal read reset MOS transistors T.sub.RHS and T.sub.RHD for resetting the video signal delivered. These horizontal read reset MOS transistors T.sub.RHS and T.sub.RHD are connected to the electrodes of the above-mentioned light signal output accumulating capacitors C.sub.S1, C.sub.S2, and C.sub.S3 and dark signal accumulating capacitors C.sub.D1, C.sub.D2, and C.sub.D3, and then to the ground (GND). Horizontal read reset MOS transistors T.sub.HRS and T.sub.HRD operate when drive pulse .phi..sub.RH, delivered from drive pulse generating circuit 43, is applied to the gate electrodes of these horizontal read reset MOS transistors T.sub.HRS and T.sub.HRD.
Horizontal select signal lines 40a, 40b, and 40c are connected to horizontal scanning circuit 40 and are connected in common for each column to each of the gate electrodes of the above-mentioned horizontal read select MOS transistors T.sub.HS1, T.sub.HS2, T.sub.HS3, T.sub.HD1, T.sub.HD2, and T.sub.HD3, and are designed such that horizontal reading is controlled by drive pulses .phi..sub.H1 to .phi..sub.H3 delivered from horizontal scanning circuit 40.
Each of the gate electrodes of the light signal output transmitting MOS transistors T.sub.S1, T.sub.S2 and T.sub.S3 is connected to drive pulse generating circuit 41 by way of light signal clock line 41a, and each of the dark output transmitting MOS transistors T.sub.D1, T.sub.D2, and T.sub.D3 is connected to drive pulse generating circuit 42 by way of dark output clock line 42a. These are designed such that when drive pulse .phi..sub.TS or .phi..sub.TD delivered from drive pulse generating circuits 41 or 42 is applied, light signal output transmitting MOS transistors T.sub.S1, T.sub.S2, and T.sub.S3 or dark output transmitting MOS transistors T.sub.D1, T.sub.D2, and T.sub.D3 operate in a predetermined sequence.
The vertical source lines 32a, 32b, and 32c are connected to the drains of reset transistors T.sub.RV1, T.sub.RV2, and T.sub.RV3 and to source-follower read constant-current sources 44a, 44b, and 44c. In addition, source voltage V.sub.RV (e.g., V.sub.RV =GND) is supplied to the sources of each reset transistor T.sub.RV1, T.sub.RV2, and T.sub.RV3, and source voltage V.sub.CS is supplied to constant-current sources 44a, 44b, and 44c.
Moreover, when reset pulse .phi..sub.RV is supplied to the gate electrodes of reset transistors T.sub.RV1, T.sub.RV2, and T.sub.RV3 and this reset pulse .phi..sub.RV is high level, vertical source lines 32a, 32b, and 32c can be conducted through reset transistors T.sub.RV1, T.sub.RV2, and T.sub.RV3 to ground (V.sub.RV =GND).
In addition, constant-current sources 44a, 44b, and 44c are designed such that by suppressing time function discrepancies due to factors such as fluctuation in the bias point for each pixel 31 at the same time that they control the time function of source follower operation, gain is systematized and fixed pattern noise (FPN) is suppressed.
Next, the operation of a photoelectric converter is explained while referring to the pulse timing chart shown in FIG. 7. The operation of reading the first row of pixels 31 is performed in the interval from t.sub.11 to t.sub.15 (the first digit of the subscript refers to the row undergoing operations). The operations of reading the second row and third rows of pixels are performed during the intervals from t.sub.21 to t.sub.25 and from t.sub.31 to t.sub.35, respectively.
In addition, each of t.sub.11 to t.sub.14 correspond as follows: t.sub.11 to the initializing operation of the JFETs 2, t.sub.12 to the source-follower operation of JFETs 2 after initializing, t.sub.13 to the operation of transmitting a signal charge from first row photodiodes 1 to JFETs 2, and t.sub.14 to the source-follower operation of JFETs 2 after transmitting. These four operations are performed during the horizontal blanking interval. Furthermore, t.sub.15 is the video signal output interval.
First, as shown in FIG. 7, at the start of interval t.sub.11, drive pulse .phi..sub.RD1 is set to high level (with drive pulses .phi..sub.RD2 and .phi..sub.RD3 still at low level), to apply a voltage drive pulse to the reset drains R.sub.D of the first row of pixels 31. Because the reset gate R.sub.G is ON (i.e., reset element 31b is p-type and .phi..sub.RG is at a low level) and a high level voltage is applied to the reset drains R.sub.D, each first row JFET 2 is selected (ON). In addition, because the reset gates R.sub.G of all pixels 31 are already conducting (ON), a low-level voltage is transmitted to the control region of the JFETs 2 of the second and third row of pixels 31, the control regions of these JFETs 2 are initialized, and each second and third row JFET 2 is not selected (OFF).
By delivering voltage drive pulses (.phi..sub.RD1, .phi..sub.RD2, and .phi..sub.RD3) to reset drains R.sub.D, JFETs 2 are selected (ON) or not selected (OFF), because the control regions of JFET 2 in selected rows are initialized at high-level potential and the control regions of JFET 2 in non-selected rows are initialized at low-level potential.
In addition, at the end of interval t.sub.11 (the start of interval t.sub.12), by setting drive pulse .phi..sub.RG to high level to make reset gate R.sub.G non-conducting (OFF), the control region of each JFET 2 is maintained at their selected (ON) or non-selected (OFF) state.
At the same time (the start of interval t.sub.12), by setting drive pulse .phi..sub.RV to low level, reset transistors T.sub.RV1 to T.sub.RV3 are intercepted (OFF). As a result, each first row JFET 2 performs source-follower operation during this interval t.sub.12.
Moreover, during this interval t.sub.12, by setting drive pulse .phi..sub.TD to high level, dark output transmitting MOS transistors T.sub.D1, T.sub.D2, and T.sub.D3 become conducting (ON), and output (dark output) voltages corresponding to the potential in the control region of each JFET 2 immediately after initializing are accumulated in dark signal accumulating capacitors C.sub.D1, C.sub.D2, and C.sub.D3.
During interval t.sub.13, by setting drive pulse .phi..sub.TG1 to low level, p-type transfer gate T.sub.G is changed from non-conducting (OFF) to conducting (ON), and by setting drive pulse .phi..sub.TS to high level and drive pulse .phi..sub.TD to low level, light signal output transmitting MOS transistors T.sub.S1, T.sub.S2, and T.sub.S3 become conducting (ON) and dark output transmitting MOS transistors T.sub.D1, T.sub.D2, and T.sub.D3 become non-conducting (OFF).
As a result, the charges generated and accumulated by the first row photodiodes 1 are transferred to the control regions of JFETs 2. Moreover, the potential in the control region of JFET 2 after this charge is transferred is changed (in this case, increased) by exactly the charge amount divided by gate capacitance. In addition, in FIG. 7, the reason why transfer gate TG becomes conducting (ON) when drive pulse .phi..sub.TG1 is low level is because transfer control element 31a is p-channel type and has the opposite polarity from the other drive pulses.
During interval t.sub.14, as in interval t.sub.12, by setting drive pulse .phi..sub.TG1 to high level, first row transfer gates TG become non-conducting (OFF) and the charge photoelectrically converted by photodiode 1 is accumulated, and by setting drive pulse .phi..sub.RV to low level, reset transistors T.sub.RV1 to T.sub.RV3 are intercepted (OFF). As a result, each first row JFET 2 performs source-follower operation.
Moreover, during this interval t.sub.14, because drive pulse .phi..sub.TS is high level, light signal output transmitting MOS transistors T.sub.S1, T.sub.S2, and T.sub.S3 become conducting (ON), and output (signal output) voltages corresponding to the potential in the control region of each JFET 2 after charge has been transmitted are accumulated in light signal output accumulating capacitors C.sub.S1, C.sub.S2, and C.sub.S3.
During interval t.sub.15, by setting each of drive pulses .phi..sub.RD1, .phi..sub.RG, and .phi..sub.TS to low level and by setting drive pulse .phi..sub.RV to high level, output voltages accumulated in light signal output accumulating capacitors C.sub.S1 to C.sub.S3 and dark signal accumulating capacitors C.sub.D1 to C.sub.D3 are prepared for output as described below.
In addition, by outputting drive pulses .phi..sub.H1 to .phi..sub.H3 from horizontal scanning circuit 40 and drive pulse .phi..sub.RH from drive pulse generating circuit 43 in sequence, signals accumulated in light signal output accumulating capacitors C.sub.S1 to C.sub.S3 and dark signal accumulating capacitors C.sub.D1 to C.sub.D3 are read by the horizontal read lines of signal output line 38 and dark output line 39, respectively. As signals are output, they are read horizontally by signal output line 38 and dark output line 39, then the horizontal read line is reset.
Moreover, signals obtained from output terminals V.sub.OS and V.sub.OD are subjected to computation processing by an external computation circuit not shown in the figure. Because the signal obtained from output terminal V.sub.OS contains a signal component (S) and a dark component (D) and the signal obtained from output terminal V.sub.OD contains only a dark component (D), by subjecting signals obtained from output terminals V.sub.OS and V.sub.OD to computation processing (subtraction processing (V.sub.OS -V.sub.OD)), a dark signal corresponding to only the signal component (S) is extracted.
First row reading operating corresponding to interval t.sub.11 to t.sub.15 described above is repeated in the same way for the second and third rows during the interval from t.sub.21 to t.sub.25 and the interval from t.sub.31 to t.sub.35.
However, a solid-state photographic element such as shown in FIG. 6 can not perform electronic shutter action simultaneously for all pixels. To perform electronic shutter action simultaneously for all pixels, photoelectric converters must be reset simultaneously for all pixels and signal charges accumulated by photoelectric converters simultaneously for all pixels must be transmitted to amplifiers simultaneously for all pixels.
However, in prior art solid-state photographic elements, a charge accumulated by a photoelectric converter (buried photodiode) is transmitted to an amplifier (JFET 2) for each row sequentially and cannot be transmitted simultaneously in all pixels. If prior art elements where set to transfer the charge simultaneously in all pixels no video signal would result because the amplifiers (JFET 2) of all pixels would be ON simultaneously and signals to light signal accumulating capacitors or dark output accumulating capacitors would be accumulated simultaneously for all pixels. To provide a video signal it is necessary to read the charges sequentially.